DICE Simulator
Date:
DICE is an open architecture-level simulation framework for detailed inter-chiplet end-to-end PHY-link modeling.
Code repository for the paper
DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
To appear in ACM/IEEE International Symposium on Computer Architecture (ISCA), 2026.
🔗 GitHub Repository
📄 arXiv Paper
📦 Artifact
Repository Contents
DICE models cross-package chiplet communication as a physical-layer-aware process rather than a fixed latency. The framework captures:
- Inter-chiplet PHY-link behavior
- Signal integrity effects
- Forward error correction and retransmission
- Latency variability and stochastic link behavior
- Architecture-level consequences of chiplet communication
How to Use
Follow the README in the GitHub repository for setup, build, and usage instructions.