DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation
In 2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA), 2026
Modern processors are increasingly built as chiplets—multiple smaller dies integrated within a single package—yet architectural simulators still treat inter-chiplet communication as a fixed latency parameter. DICE introduces detailed, end-to-end physical-layer (PHY) modeling of cross-package links, capturing signal integrity, forward error correction (FEC), channel noise, and retransmission.
We show that inter-chiplet communication cannot be reduced to a static latency: packaging-layer effects inject latency variability and stochastic behavior that fundamentally shape system-level performance, bandwidth, and even correctness. Using DICE, validated against commercial AMD chiplet processors, we observe that synchronization-intensive workloads can slow down by up to 9.53x on a chiplet-based system relative to an equivalent monolithic multicore—effects invisible to the fixed-latency models the field still uses.
DICE provides the first cross-package PHY-link modeling framework for accurate chiplet simulation, and is the scientific foundation for the NAUTILUS research programme.
Recommended citation: R. Aligholipour, S. Kaxiras and Yuan Yao, "DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation," 2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA), Raleigh, USA, 2026.
