Anatomy of the gem5 Simulator: AtomicSimpleCPU, TimingSimpleCPU, O3CPU, and Their Interaction with the Ruby Memory System
In arXiv preprint, 2025
This paper explains how gem5’s AtomicSimpleCPU, TimingSimpleCPU, and O3CPU models interact with the Ruby memory system, providing a practical basis for analyzing and extending full-system simulations.
Recommended citation: J. Söderström and Yuan Yao, "Anatomy of the gem5 Simulator: AtomicSimpleCPU, TimingSimpleCPU, O3CPU, and Their Interaction with the Ruby Memory System," arXiv:2508.18043, 2025.
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