[gem5 Q&A] Why there is miss prediction of non-control instructions
Published:
Hello, In function checkSignalsAndUpdate(ThreadID tid) in src/cpu/o3/fetch.cc file, it seems miss prediction can still happen from commit and decode even if mispredictInst->isControl() is false.
// Check squash signals from commit.
if (fromCommit->commitInfo[tid].squash) {
DPRINTF(Fetch, "[tid:%i] Squashing instructions due to squash "
"from commit.\n",tid);
// In any case, squash.
squash(*fromCommit->commitInfo[tid].pc,
fromCommit->commitInfo[tid].doneSeqNum,
fromCommit->commitInfo[tid].squashInst, tid);
// If it was a branch mispredict on a control instruction, update the
// branch predictor with that instruction, otherwise just kill the
// invalid state we generated in after sequence number
if (fromCommit->commitInfo[tid].mispredictInst &&
fromCommit->commitInfo[tid].mispredictInst->isControl()) {
branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
*fromCommit->commitInfo[tid].pc,
fromCommit->commitInfo[tid].branchTaken, tid);
} **else {
branchPred->squash(fromCommit->commitInfo[tid].doneSeqNum,
tid);
}**
return true;
}
Can someone please explain when would this else condition be true? How can there be miss prediction of non-control instructions?
My answer
Yes, because not all the squashes are caused by control instructions.
Another source of squash is memory violations (IEW::SquanshDueToMemOrder).
There, the squash bit toCommit->squash is set, but toCommit->mispredictInst is set to NULL.
Thus, when the reason for the squash is later checked in Commit::commit() and then in Fetch::checkSignalsAndUpdate, the if(fromIEW->mispredictInst[tid]) branch is not executed.
The branchPred->squash() function in the else-part is to delete all the branch predictor states that has been made after the squash instruction (BPredUnit::Squash).
Hope this helps.