Hi, I am working on the x86 page walker in gem5. I understand that the page walker accesses the page walker cache (PWC) first and, in case of a miss, it accesses the memory hierarchy (L1, then L2, then L3 caches and lastly the memory). This happens through the packetpointer read, which reads the physical address of the entry at each level (PML4, PDP.. etc.).

Now, what I would like to inquire about is how to identify where this read request for the PTE hits in the memory hierarchy. In other words, for each step, I would like to know whether this entry was a hit in L1, L2, or L3. So, is there any field or function/method in the packet that holds this information? If not, how can I get this information?

Thanks,

My answer

Hi,

I have done something similar with ruby enabled. Hope this helps.

Basically you need to set your own message flags in the pagetable walker and checks that flag in the SLICC code when a cacheline hits. Below is an example of how to do it in the L1 and L2.

in request.hh

bool isYourType() const {return _flags.isSet(your_flag);}

in pagetable_walker.cc

setupWalk(Addr vaddr){

    Request::Flags flags = Request::PHYSICAL;
    flags.set(Request::your_flag);
    ...
}

in RubyRequest.hh

book checkYourType() const { return m_pkt->req->isYourType();}

in PROTOCOL-L1Cache.sm

in_port(mandatoryQueue_in, RubyRequest ...)
    if (mandatorQueue_in.isReady(clockEdge()))
        peek(mandatoryQueue_in ...)

            if(is_valid(L1Dcache_entry))
                if(in_msg.checkYourType() == true)
                    # you have it in your local private cache
                else
                    # forward the request to L2

in PROTOCOL-L2Cache.sm

in_port(L1RequestL2Network_in, ...)
    if(L1RequestL2Network_in.isReady(clockEdge()))
        peek(L1RequestL2Network_in ...)
            if(is_valid(cache_entry))
                if(in_msg.checkYourType() == true)
                    # you have it in your shared L2
                else
                    # forward to where it should be