Yuan Yao

Assistant Professor, Computer Architecture · Uppsala University · yuan.yao@it.uu.se

CV

Education and qualifications

2026: Docent in Computer Science, Uppsala University.
2019: PhD in Computer and Electronic Systems, KTH Royal Institute of Technology. Supervisor: Professor Zhonghai Lu.
2014: MSc in System-on-Chip Design, KTH Royal Institute of Technology.
2009: BSc in Microelectronics, Northwestern Polytechnical University, China.

Positions

2020–present: Assistant Professor in Computer Systems, Department of Information Technology, Uppsala University; Uppsala Architecture Research Team (UART).
2019–2020: Postdoctoral Researcher in Computer Systems, Department of Information Technology, Uppsala University. Advisor: Professor Stefanos Kaxiras.

Funding as principal investigator

2026–2029: Swedish Research Council (VR) Starting Grant, sole principal investigator. NEAT: Interconnection Networks for Heterogeneous AI Accelerators. Link
2020: Uppsala University faculty start-up package, sole principal investigator; supporting one PhD position and associated research costs.

Teaching

2020–present: 1DT109, Accelerating Systems with Programmable Logic Components (MSc, 10 ECTS), course responsible.
2021–present: 1DT038, Computer Architecture (BSc, 5 ECTS), course responsible.
2020–2022: 1DL560, Parallel Programming for Efficiency (MSc, 5 ECTS), course responsible.

Supervision

Main supervisor: Rashid Aligholipour (2020–present).
Co-supervisor: Hannah Atmer, Shiming Li, Pavlos Aimoniotis, and Weining Song (2021–present).
MSc theses: more than 20 supervised since 2019, including industry-linked projects with SambaNova and Ericsson.

Awards and recognition

2026: HiPEAC Paper Award, ISCA, for DICE.
2024: Best Computer Architecture Track Paper, SBAC-PAD, for TangramFP.
2021: HiPEAC Paper Award, HPCA, for TSOPER.
2018: HiPEAC Paper Award and Best Paper Candidate, HPCA, for iNPG.
2016: HiPEAC Paper Award, ISCA, for OCOR.
2016: HiPEAC Paper Award, HPCA, for NoC DVFS.

Publications

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

R. Aligholipour, S. Kaxiras and Yuan Yao, "DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation," arXiv:2607.24221, 2026.

DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation

R. Aligholipour, S. Kaxiras and Yuan Yao, "DICE: Detailed Inter-Chiplet End-to-End PHY Modeling for Accurate Chiplet Simulation," 2026 ACM/IEEE 53rd Annual International Symposium on Computer Architecture (ISCA), Raleigh, USA, 2026.

NoCWalk: In-Network Page Walks for Concurrent Data Structure Workloads on Multicore

Yuan Yao, S. Li, R. Aligholipour and S. Kaxiras, "NoCWalk: In-Network Page Walks for Concurrent Data Structure Workloads on Multicore," 2026 ACM International Conference on Computing Frontiers (CF), Catania, Italy, 2026.

ConvReflex: Efficient Ultra-Low-Power CNN Inference via Clamping Prediction

S. Li, L. Mottola, Yuan Yao and S. Kaxiras, "ConvReflex: Efficient Ultra-Low-Power CNN Inference via Clamping Prediction," ACM/IEEE International Conference on Embedded Artificial Intelligence and Sensing Systems (SenSys), Saint-Malo, France, 2026.

Understanding Simulated Architecture via gem5 Call-Stack Profiling

J. Söderström, R. Aligholipour and Yuan Yao, "Understanding Simulated Architecture via gem5 Call-Stack Profiling," 2026 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Seoul, South Korea, 2026.

Prefill vs. Decode Bottlenecks: SRAM-Frequency Tradeoffs and the Memory-Bandwidth Ceiling

H. Atmer, Yuan Yao, T. Voigt, and S. Kaxiras, "Prefill vs. Decode Bottlenecks: SRAM-Frequency Tradeoffs and the Memory-Bandwidth Ceiling," arXiv:2512.22066, 2025.

The Fake-Busy and True-Idle Problems of Running Graph Applications on Chiplet-Based Multi-Cores

R. Aligholipour and Yuan Yao, "The Fake-Busy and True-Idle Problems of Running Graph Applications on Chiplet-Based Multi-Cores," 2025 IEEE International Symposium on Workload Characterization (IISWC), Irvine, USA, 2025.

Anatomy of the gem5 Simulator: AtomicSimpleCPU, TimingSimpleCPU, O3CPU, and Their Interaction with the Ruby Memory System

J. Söderström and Yuan Yao, "Anatomy of the gem5 Simulator: AtomicSimpleCPU, TimingSimpleCPU, O3CPU, and Their Interaction with the Ruby Memory System," arXiv:2508.18043, 2025.

RXT: RefleXive address Translation for Pointer-Chasing Workloads

R. Aligholipour, P. Aimoniotis, S. Kaxiras and Yuan Yao, "RXT: RefleXive address Translation for Pointer-Chasing Workloads," 39th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Milan, Italy, 2025.

TangramFP: Energy-Efficient, Bit-Parallel, Multiply-Accumulate for Deep Neural Networks

Yuan Yao, X. Chen, H. Atmer and S. Kaxiras, "TangramFP: Energy-Efficient, Bit-Parallel, Multiply-Accumulate for Deep Neural Networks," 2024 IEEE 36th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Hilo, HI, USA, 2024, pp. 1-12, doi: 10.1109/SBAC-PAD63648.2024.00009.

TaDA: Task Decoupling Architecture for the Battery-less Internet of Things

Weining Song, Stefanos Kaxiras, Thiemo Voigt, Yuan Yao, and Luca Mottola. 2024. TaDA: Task Decoupling Architecture for the Battery-less Internet of Things. In Proceedings of the 22nd ACM Conference on Embedded Networked Sensor Systems (SenSys). Association for Computing Machinery, New York, NY, USA, 409–421. https://doi.org/10.1145/3666025.3699347

Silent Stores in the Battery-less Internet of Things: A Good Idea?

Weining Song, Stefanos Kaxiras, Luca Mottola, Thiemo Voigt, and Yuan Yao, ''Silent Stores in the Battery-less Internet of Things: A Good Idea?'' in Proceedings of the 2023 International Conference on embedded Wireless Systems and Networks (EWSN), Association for Computing Machinery, New York, NY, USA, 40-45.

SE-CNN: Convolution Neural Network Acceleration via Symbolic Value Prediction

Yuan Yao, "SE-CNN: Convolution Neural Network Acceleration via Symbolic Value Prediction," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, pp. 73-85, March 2023, doi: 10.1109/JETCAS.2023.3244767.

Game-of-Life Temperature-Aware DVFS Strategy for Tile-based Chip Many-Core Processor

Yuan Yao, "Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core Processors," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 13, no. 1, pp. 58-72, March 2023, doi: 10.1109/JETCAS.2023.3244763

TSOPER: Efficient Coherence-Based Strict Persistency

P. Ekemark, Yuan Yao, A. Ros, K. Sagonas and S. Kaxiras, "TSOPER: Efficient Coherence-Based Strict Persistency," 2021 IEEE International Symposium on High-Performance Computer Architecture (HPCA), Seoul, Korea (South), 2021, pp. 125-138, doi: 10.1109/HPCA51647.2021.00021.

Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS

Yuan Yao and Z. Lu, "Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS," in IEEE Transactions on Computers, vol. 69, no. 3, pp. 410-426, 1 March 2020, doi: 10.1109/TC.2019.2949807.

Thread Voting DVFS for Manycore NoCs

Z. Lu and Yuan Yao, "Thread Voting DVFS for Manycore NoCs," in IEEE Transactions on Computers, vol. 67, no. 10, pp. 1506-1524, 1 Oct. 2018, doi: 10.1109/TC.2018.2827039.

iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores

Yuan Yao and Z. Lu, "iNPG: Accelerating Critical Section Access with In-network Packet Generation for NoC Based Many-Cores," 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), Vienna, 2018, pp. 15-26, doi: 10.1109/HPCA.2018.00012.

Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS

Z. Lu and Yuan Yao, "Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS," in IEEE Transactions on Computers, vol. 66, no. 11, pp. 1903-1917, 1 Nov. 2017, doi: 10.1109/TC.2017.2715018.

Dynamic Traffic Regulation in NoC-Based Systems

Z. Lu and Yuan Yao, "Dynamic Traffic Regulation in NoC-Based Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 2, pp. 556-569, Feb. 2017, doi: 10.1109/

Aggregate Flow-Based Performance Fairness in CMPs

Zhonghai Lu and Yuan Yao. 2016. Aggregate Flow-Based Performance Fairness in CMPs. ACM Trans. Archit. Code Optim. 13, 4, Article 53 (December 2016), 27 pages. https://doi.org/10.1145/3014429

Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs

Yuan Yao and Z. Lu, "Opportunistic Competition Overhead Reduction for Expediting Critical Section in NoC Based CMPs," 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), Seoul, Korea (South), 2016, pp. 279-290, doi: 10.1109/ISCA.2016.33.

Service

Programme Committee: ISCA 2025 and 2026; HPCA 2026; ISPASS 2025 and 2026.
External reviewer: MICRO 2025 and HPCA 2024; journal reviewer for IEEE Transactions on Computers and ACM TACO.
Organizing Committee: HPCA 2022, submission co-chair.